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Silicon on Insulator CMOS Technology

Silicon on Insulator CMOS Technology

The insulating layer of silicon dioxide (SiO2) isolates the integrated circuit transistors from the bulk substrate providing a number of benefits.

Key to the silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) is the insulating layer of silicon dioxide (SiO2) isolating the integrated circuit transistors from the bulk substrate. This feature has a number of benefits:

  • Low leakage current to substrate enables greatly improved circuit operation to 225°C continuous and excursions to 300°C
  • Reduced capacitance for faster and lower power circuits
  • Greatly reduced noise with isolation from the bulk silicon for sensitive mixed signal circuits

At extreme temperatures, the packaging and assembly are critical to the reliability of the product. We employ methods and materials to ensure quality and reliability for harsh environments. We provide a wide variety of packages for your application specific integrated circuits(ASIC), many of which are qualified to MIL-PRF-38535 and screened to MIL-STD-883 for extreme environments.

The robust packaging materials and methods also apply to multi-chip modules (MCM). We have implemented designs with over 20 chips in one package.

High levels of integration can be achieved through the HT2000 gate array technology. This can incorporate up to 290k gates of usable gates. The technology also supports analog and mixed signal designs.

Using a formal phase-gate process, we assure the reliability of the SOI CMOS and products. This approach includes adhering to our general manufacturing standards for:

  • Designing in reliability by establishing electrical rules based on wear out mechanism characterization performed on specially designed test structures (electromigration, time dependent dielectric breakdown (TDDB), hot carriers, negative bias temperature instability, radiation)
  • Utilizing a structured and controlled design process
  • A statistically controlled wafer fabrication process with a continuous defect reduction process
  • Individual wafer lot acceptance through process monitor testing
  • The use of characterized and qualified packages and assembly methods all parts are burned in at 250°C

Data collection of reliability at the component level has indicated the ability to operate within specification for 5 years or more at 225° C.

The adaptation of these SOI components with high temperature design techniques can provide dramatic improvements in the reliability and lifetime of intelligent completions. Over 2.5 million device hours of life testing have been completed at temperatures ranging from 250° C to 300° C.